Computer Architecture

The Hack computer

∙Instruction memory(ROM)

∙Memory(RAM)

-Data memory

-Screen (memory map)

-Keyboard (memory map)

∙CPU

∙Computer

Memory Implementation

RAM:16-bit/16K RAM chip (already built in Chapter3)

Screen:16-bit/8K memory chip with a raster display side-effect

Screen chip(given):

CHIP Screen {

    IN  in[16],    // what to write
    load,          // write-enable bit
    address[13];   // where to read/write
    OUT out[16];   // Screen value at the given address

    BUILTIN Screen;
    CLOCKED in, load;
}

Keyboard:16-bit register with a keyboard site effect

Keyboard chip(given):

CHIP Keyborad{
    OUT out[16];    //The ASCII code of the pressed key,or 0 if no key is currently pressed,or one the special codes listed in Figure 5.5.
    BUILTIN keyboard;
}

CHIP Memory:

CHIP Memory {
    IN in[16], load, address[15];
    OUT out[16];

    PARTS:

    DMux4Way(in=load,sel=address[13..14],a=ram,b=rram,c=scrn,d=keybd);

    Or(a=ram,b=rram,out=rr);
    RAM16K(in=in,load=rr,address=address[0..13],out=r);

    Screen(in=in,load=scrn,address=address[0..12],out=sc);

    Keyboard(out=k);

    Mux4Way16(a=r,b=r,c=sc,d=k,sel=address[13..14],out=out);

}

CHIP CPU:

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M? 
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    // 111 a cccccc ddd jjj

    // i  _  _  a  c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3
    // 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

    // A instruction
    // @3001
    // [0]000101110111001
    // Op - Instruction
    // Op code of 0 means, a instruction.
    Not(in=instruction[15], out=notOp);
    Mux16(a=aluOut, b=instruction, sel=notOp, out=entryMuxOut);

    Or(a=notOp, b=instruction[5], out=intoA);
    ARegister(in=entryMuxOut, load=intoA, out=A, out[0..14]=addressM);

    // C instruction
    // Op code is 1, indexes:
    // 15 - Op code
    // 12-14 ???
    // 6-11 ALU control bits
    // 3-5 Destination load bits
    // 0-2 Jump bits
    //
    // ALU takes input from DRegister and from ARegister or inM
    And(a=instruction[15], b=instruction[12], out=AMSwitch);
    Mux16(a=A, b=inM, sel=AMSwitch, out=AM);

    And(a=instruction[15], b=instruction[4], out=intoD);
    DRegister(in=aluOut,load=intoD, out=D);

    ALU(x=D, y=AM, out=aluOut, out=outM,
        zx=instruction[11],
        nx=instruction[10],
        zy=instruction[9],
        ny=instruction[8],
        f=instruction[7],
        no=instruction[6],

        zr=zrOut,
        ng=ngOut
    );

    // writeM uses 3rd destination load bit.
    And(a=instruction[15], b=instruction[3], out=writeM);

    // Program counter.
    // Emits next instruction.
    // Reset: = 0
    // 000 nojump: ++
    // 111 goto: = A
    // 010 100 etc conditional goto: = A || ++
    Not(in=ngOut, out=pos);
    Not(in=zrOut, out=nzr);
    And(a=instruction[15], b=instruction[0], out=jgt);
    And(a=pos, b=nzr, out=posnzr);
    And(a=jgt, b=posnzr, out=ld1);

    And(a=instruction[15], b=instruction[1], out=jeq);
    And(a=jeq, b=zrOut, out=ld2);

    And(a=instruction[15], b=instruction[2], out=jlt);
    And(a=jlt, b=ngOut, out=ld3);

    Or(a=ld1, b=ld2, out=ldt);
    Or(a=ld3, b=ldt, out=ld);

    PC(in=A, load=ld, inc=true, reset=reset, out[0..14]=pc);
}

Computer:

CHIP Computer {

    IN reset;

    PARTS:

    ROM32K(address=pc,out=instruction);

    CPU(inM=inM,instruction=instruction,reset=reset,outM=outM,writeM=writeM,addressM=addressM,pc=pc);

    Memory(in=outM,load=writeM,address=addressM,out=inM);


}